Description of the Related Art
Digital Signal Processing (DSP) algorithms often utilize multiply-accumulate (MAC) intensive operations. Typical multiple-accumulate operations include multiple steps and utilize extensive resources. First, a full scale negative test is performed where if both a first operand and a second operand are full scale negative values, the result is set to a full scale positive operand. Otherwise, the first and second operands are multiplied together. The product is left shifted by one bit, accumulated with a previous result, and saturated if needed.
The multiple steps required to implement a multiply-accumulate operation can often be folded into a single instruction. A typical DSP implementation may include a dual multiply-accumulate unit that provides 16 possible combinations of four loaded operands which are presented to two multipliers. However, some of the most common algorithms only require a few of these possible combinations. Providing multiply-accumulators with such flexibility may be costly in terms of space and instruction coding complexity.
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